1. Field of The Invention
The present invention relates in general to a repair circuit for repairing storage cells in an integrated storage device, memory cells having a fault, and more particularly to a repair circuit for in-L,(? grated circuits which is capable of reducing power consumption therein by switching off unnecessary current incoming thereinto.
1. Description of the Prior Art
In design of a storage device, conventionally, there has been desired that a repair circuit should repair storage cells having a fault for the purpose of integration of the storage device allowing many information to be stored in one chip and therefore of its set-up in yield.
Referring to FIG. 1, a conventional repair circuit is shown to comprise a repair means 1 including a plurality of p-channel MOSFETs P1-Pn and a plurality of fuses FP1-FPn coupled parallel to the p-channel MOSFETs P1-Pn for selecting and repairing a storage cell having a fault. Each gate of the p-channel MOSFETs P1-Pn is adapted to input an address decoding output and each drain thereof is connected to the fuses FP1- FPn. Also, the above-mentioned conventional repair circuit comprises a main fuse means 2 adapted for operating the repair means 1 upon detecting an address for the cell having the fault, a pair of n-channel MOSFETs T1 and T2 connected to the repair means 1 and adapted for operating in accordance with an output from the main fuse means 2, and an inverter G3 connected to an output stage of the repair means 1 for outputting a signal REDY.
Now, the operation of the above-mentioned conventional repair circuit will be described.
First, upon detecting an address for a cell having a fault, fuses F1 and F2 in the main fuse means 2 are cut to operate the repair means 1. Then, of fuses FP1-FPn connected to p-channel MOSFETs P1-Pn in the repair means 1, fuses connected to p-channel MOSFETs in which gates input an address decoding output for a cell having no fault are cut, while fuses connected to p-channel MOSFETs in which gates input an address decoding output for the cell having fault are maintained naturally. As the fuses F1 and F2 in the main fuse means 2 are cut, an output signal A from the main fuse means 2 always is at a high state enabling the n-channel MOSFETs T1 and T2 in which each gate inputs the output signal A from the main fuse means 2 to be at ON state. Therefore, if the address for cell having fault is selected, the decoding output at a low state goes to a high state enabling an output signal B from the repair means 1 to be made a low state. Finally, the output signal B at the low state is inverted into a high state by the inverter G3 which then outputs a high signal REDY into which the output signal B was inverted thereby, thereby allowing the cell having fault to be repaired.
In the conventional repair circuit as mentioned above, however, when an address for a cell having no fault is selected after said repairing step, the decoding output at a high state goes to a low state enabling p-channel MOSFETs P1-Pn for the uncut fuses in which each gate inputs the decoding output at the low state to be made ON state since fuses connected to the p-channel MOSFETs in which gates input the address decoding output for cell having no fault are not cut, thereby allowing current to flow through the n-channel MOSFETs T1 and T2 in operation. Unfortunately, this current flow results in unnecessary power consumption in the repair circuit.